1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device with a memory cell of a floating gate type, specifically relates to a method of controlling read/write of a NAND-type flash memory.
2. Description of the Related Art
A currently manufactured NAND-type flash memory has floating gate type of memory cells, write and erase of which are performed with electron-injection and electron-releasing of the respective floating gates (FGs). Controlling the electron injection quantity in a floating gate, it is able to set multiple threshold voltage states (i.e., data states). In practice, it has been achieved such a NAND-type flash memory that stores four level data (i.e., stores two bits per cell).
What becomes problematic when the NAND-type flash memory is more highly integrated and stores more data bits per cell is an interference noise between floating gates. This interference effect is defined as follows: assuming that a memory cell Cell_A is written, and then adjacent memory cell Cell_B is written, FG potential of Cell_A is influenced by the change of FG potential of Cell_B to be changed, so that the threshold distribution appears to be widened.
There has been proposed a write control scheme preferable for making the interference between cells less (refer to, for example, JP-A-2005-243205). In this write control scheme, it is not used such an upper page write mode that brings straight the lowermost level of four levels to the uppermost level. As a result, the interference noise between cells will be reduced. Additionally, in the write control scheme, word lines are basically selected in order from the source line side, and word line selecting orders of the lower page write and the upper page write are suitably combined so as to reduce the influence between cells.
However, as the highly integration of the NAND-type flash memories progresses, there is possibility that it becomes difficult to avoid the interference noise between adjacent cells.